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| 19-4437; Rev 0; 2/09 KIT ATION EVALU ABLE AVAIL Low-Jitter Frequency Synthesizer with Selectable Input Reference General Description Features Two Reference Clock Inputs: LVPECL Nine Phase-Aligned Clock Outputs: LVPECL Input Frequencies: 62.5MHz,125MHz, 250MHz, 312.5MHz Output Frequencies: 62.5MHz, 125MHz, 156.25MHz, 250MHz, 312.5MHz Low-Jitter Generation: 0.3psRMS (12kHz to 20MHz) Clock Failure Indicator for Both Reference Clocks External Feedback Provides Zero-Delay Capability Low Output Skew: 20ps Typical MAX3671 The MAX3671 is a low-jitter frequency synthesizer that accepts two reference clock inputs and generates nine phase-aligned outputs. The device features 40kHz jitter transfer bandwidth, 0.3psRMS (12kHz to 20MHz) integrated phase jitter, and best-in-class power-supply noise rejection (PSNR), making it ideal for jitter cleanup, frequency translation, and clock distribution in Gigabit Ethernet applications. The MAX3671 operates from a single +3.3V supply and typically consumes 400mW. The IC is available in an 8mm x 8mm, 56-pin TQFN package, and operates from -40C to +85C. Applications Gigabit Ethernet Routers and Switches Frequency Translation Jitter Cleanup Clock Distribution Pin Configuration and Typical Application Circuits appear at end of data sheet. PART MAX3671ETN+ Ordering Information TEMP RANGE -40C to +85C PIN-PACKAGE 56 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Functional Diagram SEL_CLK DM CPLL 0.1F CREG 0.22F DA PLL_BYPASS OUTA_EN REFCLK0 0 REFCLK0 REFCLK1 1 REFCLK1 DIV M PFD 62.5MHz CP VCO 2.5GHz DIV A 1 0 OUTA3 OUTA3 OUTA2 OUTA2 OUTA1 IN0FAIL IN1FAIL LOCK DIV N POWER-ON RESET (POR) 1 DIV B 0 SIGNAL QUALIFIER AND LOCK DETECT OUTA1 OUTA0 OUTA0 OUTB_EN MR OUTB4 OUTB4 OUTB3 OUTB3 OUTB2 1 MAX3671 0 OUTB2 OUTB1 OUTB1 OUTB0 OUTB0 FB_SEL FB_IN FB_IN DB ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. Low-Jitter Frequency Synthesizer with Selectable Input Reference MAX3671 ABSOLUTE MAXIMUM RATINGS Supply Voltage Range (VCC, VCC_VCO)..............-0.3V to +4.0V LVPECL Output Current (OUTA[3:0], OUTA[3 : 0], OUTB[4:0], OUTB[4 : 0]) .............................-56mA All Other Pins..............................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 56-Pin TQFN (derate 47.6mW/C above 70C)..........3808mW Operating Junction Temperature (TJ)................-55C to +150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40C to +85C, CPLL = 0.1F, CREG = 0.22F. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) PARAMETER Supply Current POWER-ON RESET VCC Rising VCC Falling Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage VIH VIL I IH I IL VOH VOL VIN = VCC VIN = GND I OH = -8mA I OL = +8mA -75 2.4 0.4 VCC 0.7 VCC 2.0 VCC 1.8 0.15 > 40 > 14 1.5 VIH = VCC - 0.7V, VIL = VCC - 2.0V IDC (Notes 3, 4) -100 8 6 +100 VCC 1.34 1.9 (Note 1) (Note 1) 2.0 0.8 75 2.55 2.45 V V V V A A V V SYMBOL ICC CONDITIONS LVPECL outputs unterminated MIN TYP 120 MAX 175 UNITS mA LVCMOS/LVTTL INPUTS (MR, SEL_CLK, PLL_BYPASS, FB_SEL) LVCMOS/LVTTL OUTPUTS (IN0FAIL, IN1FAIL, LOCK) LVPECL INPUTS (REFCLK0, REFCLK0, REFCLK1, REFCLK1, FB_IN, FB_IN) (Note 2) Input High Voltage Input Low Voltage Input Bias Voltage Differential-Input Swing Differential-Input Impedance Common-Mode Input Impedance Input Capacitance Input Current Input Inrush Current When Power is Off (Steady State) Input Inrush Current Overshoot When Power is Off VIH VIL VCMI V V V VP-P k k pF A mA mA IOVERSHOOT (Notes 3, 4) 2 _______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Selectable Input Reference ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = -40C to +85C, CPLL = 0.1F, CREG = 0.22F. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) PARAMETER Reference Clock Frequency Reference Clock Frequency Tolerance Reference Clock Duty Cycle Reference Clock Amplitude Detection Assert Threshold VDT Differential swing (Notes 5, 6) SYMBOL fREF -200 40 200 CONDITIONS MIN TYP Table 1 +200 60 MAX UNITS MHz ppm % mVP-P REFERENCE CLOCK INPUTS (REFCLK0, REFCLK0, REFCLK1, REFCLK1) MAX3671 LVPECL OUTPUTS (OUTA[3:0], OUTA[3:0], OUTB[4:0], OUTB[4:0]) (Note 7) Output High Voltage Output Low Voltage Differential-Output Swing Output Current When Disabled Output Frequency Output Rise/Fall Time Output Duty Cycle Output-to-Output Skew t SKEW f OUT tR, tF 20% to 80% (Note 8) PLL_BYPASS = 0 PLL_BYPASS = 1 (Note 9) Within output bank All outputs 150 48 45 20 40 40 0.1 62.5 2.5 Integrated 12kHz to 20MHz (Notes 5, 8) (Note 10) 0.3 5 1.0 VO = VCC - 2.0V to VCC - 0.7V Tables 2, 3 500 52 55 VOH VOL VCC 1.13 VCC 1.85 1.1 VCC 0.98 VCC 1.70 1.45 VCC 0.83 VCC 1.55 1.8 130 V V VP-P A MHz ps % ps OTHER AC ELECTRICAL SPECIFICATIONS PLL Jitter Transfer Bandwidth Jitter Peaking PFD Compare Frequency VCO Center Frequency Random Jitter Generation Determinisitic Jitter Caused by Power-Supply Noise Frequency Difference Between Reference Clock and VCO Within Which the PLL is Considered in Lock Frequency Difference Between Reference Clock and VCO at Which the PLL is Considered Out-of-Lock PLL Lock Time tLOCK Figure 2 kHz dB MHz GHz psRMS psP-P 500 ppm 800 ppm 600 s _______________________________________________________________________________________ 3 Low-Jitter Frequency Synthesizer with Selectable Input Reference MAX3671 ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = -40C to +85C, CPLL = 0.1F, CREG = 0.22F. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) PARAMETER Master Reset (MR) Minimum Pulse Width Propagation Delay from Input to FB_IN Propagation Delay from Input to Any Output FB_SEL = 1 (Notes 8, 11) PLL_BYPASS = 1 -120 1.0 SYMBOL CONDITIONS MIN TYP 100 +120 MAX UNITS ns ps ns During the power-on-reset time, the LVPECL outputs are held to logic-low (OUTxx = low, OUTxx = high). See the PowerOn-Reset (POR) section for more information. Note 2: LVPECL inputs can be AC- or DC-coupled. Note 3: For hot-pluggable purposes, the device can receive LVPECL inputs when no supply voltage is applied. Measured with VCC pins connected to GND. See Figure 1. Note 4: Measured with LVPECL input (VIH, VIL) as specified. Note 5: Measured using reference clock input with 550ps rise/fall time (20% to 80%). Note 6: When input differential swing is below the specified threshold, a clock failure is declared. See Figure 4. Note 7: LVPECL outputs terminated 50 to VTT = VCC - 2V. Note 8: Guaranteed by design and characterization. Note 9: Measured with 50% duty cycle at reference clock input. Note 10: Measured with 50mVP-P sinusoidal noise on the power supply, fNOISE = 100kHz. Note 11: Measured with fREFCLKx = fFB_IN and matched slew rates. Note 1: 4 _______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Selectable Input Reference MAX3671 INRUSH CURRENT (mA) IOVERSHOOT IDC t Figure 1. LVPECL Input Inrush Current VCC POWER-ON-RESET (~ 20s) REFCLK0 REFCLK1 OUTxx IN0FAIL HIGH IN1FAIL HIGH LOCK tLOCK (~ 600s) PLL LOCKED TO REFCLK0 SEL_CLK LOW Figure 2. Power-Up, PLL Locks to REFCLK0 _______________________________________________________________________________________ 5 Low-Jitter Frequency Synthesizer with Selectable Input Reference MAX3671 Typical Operating Characteristics (VCC = 3.3V, TA = +25C, unless otherwise noted.) PHASE NOISE AT 62.5MHz MAX3671 toc01 PHASE NOISE AT 125MHz MAX3671 toc02 PHASE NOISE AT 156.25MHz -70 -80 PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 RANDOM JITTER = 0.28psRMS INTEGRATED 12kHz TO 20MHz MAX3671 toc03 -60 -70 -80 PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 RANDOM JITTER = 0.41psRMS INTEGRATED 12kHz TO 20MHz -60 -70 -80 PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 RANDOM JITTER = 0.29psRMS INTEGRATED 12kHz TO 20MHz -60 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (Hz) OFFSET FREQUENCY (Hz) OFFSET FREQUENCY (Hz) PHASE NOISE AT 250MHz MAX3671 toc04 PHASE NOISE AT 312.5MHz -70 -80 PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 -25 -30 100 1k 10k 100k 1M 10M 100M 1k RANDOM JITTER = 0.28psRMS INTEGRATED 12kHz TO 20MHz MAX3671 toc05 JITTER TRANSFER MAX3671 toc06 -60 -70 -80 PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 RANDOM JITTER = 0.27psRMS INTEGRATED 12kHz TO 20MHz -60 5 0 JITTER TRANSFER (dB) -5 -10 -15 -20 100 1k 10k 100k 1M 10M 100M 10k 100k 1M OFFSET FREQUENCY (Hz) OFFSET FREQUENCY (Hz) JITTER FREQUENCY (Hz) DIFFERENTIAL OUTPUT WAVEFORM AT 156.25MHz MAX3671 toc07 DIFFERENTIAL OUTPUT WAVEFORM AT 312.5MHz MAX3671 toc08 REFERENCE CLOCK AMPLITUDE DETECTION ASSERT THRESHOLD vs. INPUT FREQUENCY 280 ASSERT THRESHOLD (mVP-P) 260 240 220 200 180 160 140 120 100 INPUT RISE/FALL TIME = 270ps INPUT RISE/FALL TIME = 550ps MAX3671 toc09 300 200mV/div 200mV/div 800ps/div 400ps/div 50 100 150 200 250 300 350 REFERENCE CLOCK INPUT FREQUENCY (MHz) 6 _______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Selectable Input Reference Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25C, unless otherwise noted.) MAX3671 SUPPLY CURRENT vs. TEMPERATURE 450 400 SUPPLY CURRENT (mA) 350 300 250 200 150 100 50 0 -40 -15 10 35 60 85 ALL OUTPUTS ENABLED AND UNTERMINATED ALL OUTPUTS ENABLED AND TERMINATED MAX3671 toc10 JITTER HISTOGRAM WITH SUPPLY NOISE (SUPPLY NOISE = 50mVP-P, 100kHz) MAX3671 toc11 DETERMINISTIC JITTER vs. POWER-SUPPLY NOISE AMPLITUDE 35 DETERMINISTIC JITTER (psP-P) 30 25 20 15 10 5 0 0 50 100 150 200 250 300 fNOISE = 1MHz fNOISE = 200kHz fNOISE = 100kHz MAX3671 toc12 500 40 DJ = 5psP-P 2ps/div TEMPERATURE (C) SUPPLY NOISE AMPLITUDE (mVP-P) SPURS CAUSED BY POWER-SUPPLY NOISE vs. SUPPLY NOISE FREQUENCY MAX3671 toc13 DETERMINISTIC JITTER vs. POWER-SUPPLY NOISE FREQUENCY 35 DETERMINISTIC JITTER (psP-P) 30 SUPPLY NOISE = 100mVP-P 25 20 15 10 5 0 SUPPLY NOISE = 50mVP-P LOCK OUTxx MAX3671 toc14 POWER-ON-RESET MAX3671 toc15 0 -10 -20 SPUR POWER (dBc) -30 -40 -50 -60 -70 -80 -90 -100 fOUT = 125MHz 40 VCC SUPPLY NOISE = 100mVP-P SUPPLY NOISE = 50mVP-P 10k 100k 1M 10M 10k 100k 1M 10M 200s/div SUPPLY NOISE FREQUENCY (Hz) SUPPLY NOISE FREQUENCY (Hz) MASTER RESET MAX3671 toc16 REFERENCE CLOCK FAILURE DETECTION MAX3671 toc17 MR REFCLK1 OUTxx IN1FAIL LOCK LOCK 40s/div 2ms/div _______________________________________________________________________________________ 7 Low-Jitter Frequency Synthesizer with Selectable Input Reference MAX3671 Pin Description PIN 1 2 3 4 5 6 7, 22, 30, 41, 49, 52 8, 14, 23, 29, 42, 48, 53 NAME IN0FAIL RSVD1 RSVD2 REFCLK0 REFCLK0 DM VCC GND FUNCTION REFCLK0 Failure Indicator, LVCMOS/LVTTL Output. Low indicates REFCLK0 fails the clock qualification. Once a failed clock is detected, the indicator status is latched and updated every 128 PFD cycles (~ 2s). Reserved. Leave pin open. Reserved. Connect to GND. Reference Clock Input 0, Differential LVPECL Four-Level Control Input for Reference Clock Input Divider. See Table 1. Power Supply. Connect to +3.3V. Supply Ground Master Reset, LVCMOS/LVTTL Input. Connect this pin high or leave open for normal operation. Has internal 90k pullup to VCC. Connect low to reset the device. A reset is not required at power-up. If the output divider settings are changed on the fly, a reset is required to phase align the outputs. This input has a 100ns minimum pulse width and is asynchronous to the reference clock. While in reset, all clock outputs are held to logiclow. See Table 6. Reference Clock Input 1, Differential LVPECL Reference Clock Select, LVCMOS/LVTTL Input. Connect low or leave open to select REFCLK0 as the reference clock. Has internal 90k pulldown to GND. Connect high to select REFCLK1 as the reference clock. Power Supply for VCO. Connect to +3.3V. Connection for PLL Filter Capacitor. Connect a 0.1F capacitor between this pin and GND. Connection for VCO Regulator Capacitor. Connect a 0.22F capacitor between this pin and GND. External Feedback Select, LVCMOS/LVTTL Input. Connect high to select external feedback for zero-delay buffer configuration. Connect low or leave open for internal feedback. Has internal 90k pulldown to GND. External Feedback Clock Input, Differential LVPECL. Used for zero-delay buffer configuration. Clock Output B0, Differential LVPECL Clock Output B1, Differential LVPECL Clock Output B2, Differential LVPECL Four-Level Control Input for B-Group Output Divider. See Table 3. Clock Output B3, Differential LVPECL Clock Output B4, Differential LVPECL Three-Level Control Input for B-Group Output Enable. See Table 5. Three-Level Control Input for A-Group Output Enable. See Table 4. 9 MR 10 11 12 13 15 16 REFCLK1 REFCLK1 SEL_CLK VCC_VCO CPLL CREG 17 18 19 20 21 24 25 26 27 28 31 32 33 34 35 36 FB_SEL FB_IN FB_IN OUTB0 OUTB0 OUTB1 OUTB1 OUTB2 OUTB2 DB OUTB3 OUTB3 OUTB4 OUTB4 OUTB_EN OUTA_EN 8 _______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Selectable Input Reference Pin Description (continued) PIN 37 38 39 40 43 44 45 46 47 NAME OUTA3 OUTA3 OUTA2 OUTA2 DA OUTA1 OUTA1 OUTA0 OUTA0 Clock Output A3, Differential LVPECL Clock Output A2, Differential LVPECL Four-Level Control Input for A-Group Output Divider. See Table 2. Clock Output A1, Differential LVPECL Clock Output A0, Differential LVPECL PLL Bypass Control, LVCMOS/LVTTL Input. Connect low or open for normal operation. Has internal 90k pulldown to GND. Connect high to bypass the PLL, connecting the selected reference clock directly to the clock outputs. In this mode, the clock qualification function is not valid. To reduce spurious jitter in bypass mode, the internal VCO should be disabled by shorting the CREG pin to GND. Reserved. Connect to VCC. Reserved. Leave pin open. PLL Lock Indicator, LVCMOS/LVTTL Output. Low indicates PLL is locked. REFCLK1 Failure Indicator, LVCMOS/LVTTL Output. Low indicates REFCLK1 fails the clock qualification. Once a failed clock is detected, the indicator status is latched and updated every 128 PFD cycles (~ 2s). Exposed Pad. Connect to supply ground for proper electrical and thermal performance. FUNCTION MAX3671 50 PLL_BYPASS 51 54 55 56 -- RSVD3 RSVD4 LOCK IN1FAIL EP Detailed Description The MAX3671 integrates two differential LVPECL reference inputs with a 2:1 mux, a PLL with configurable dividers, nine differential LVPECL clock outputs, and a selectable external feedback input for zero-delay buffer applications (see the Functional Diagram). The two reference clock inputs are continuously monitored for clock failure by the internal PLL and associated logic. If the primary clock fails, the user can switch over to the secondary clock using the 2:1 mux. The PLL accepts reference input frequencies of 62.5, 125, 250, or 312.5MHz and generates output frequencies of 62.5, 125, 156.25, 250, or 312.5MHz. The nine clock outputs are organized into two groups (A and B). Each group has a configurable frequency divider and output-enable control. divided reference frequency to the divided VCO output at 62.5MHz, and generates a control signal to keep the VCO phase and frequency locked to the selected reference clock. Using a high-frequency VCO (2.5GHz) and low-loop bandwidth (40kHz), the MAX3671 attenuates reference clock jitter while maintaining lock and generates low-jitter clock outputs at multiple frequencies. Typical jitter generation is 0.3psRMS (integrated 12kHz to 20MHz). To minimize supply noise-induced jitter, the VCO supply (VCC_VCO) is isolated from the core logic and output buffer supplies. Additionally, the MAX3671 uses an internal low-dropout (LDO) regulator to attenuate noise from the power supply. This allows the device to achieve excellent power-supply noise rejection, significantly reducing the impact on jitter generation. Clock Failure Conditions The MAX3671 clock failure detection is performed using the combination of amplitude qualification and PLL frequency and phase-error qualification. The failure status is indicated for REFCLK0 and REFCLK1 at Phase-Locked Loop (PLL) The PLL contains a phase-frequency detector (PFD), charge pump (CP) with a lowpass filter, and voltagecontrolled oscillator (VCO). The PFD compares the _______________________________________________________________________________________ 9 Low-Jitter Frequency Synthesizer with Selectable Input Reference MAX3671 IN0FAIL and IN1FAIL, respectively. Once an indicator is asserted low, it is latched and updated every 128 PFD cycles (~ 2s). It should be noted that when the PLL is locked to a reference clock, the clock failure indicator for the other reference clock is only valid for amplitude qualification and frequency qualification. BOTH INPUTS OPEN 130 VCC 130 VCC MAX3671 Amplitude Qualification A reference clock input fails amplitude qualification if any of the following conditions occur: * Either one or both inputs (REFCLKx, REFCLKx) are shorted to VCC or GND. * Both inputs (REFCLKx, REFCLKx) are disconnected from the source and have 130 to VCC and 82 to GND at each input. See Figure 3. * Input reference clock differential swing is below the clock failure assert threshold as specified in the Electrical Characteristics. See Figure 4. The response time for these conditions is typically between 50ns and 300ns. 82 82 LVPECL Figure 3. Positions for Open-Circuit Detection DIFFERENTIAL INPUT: (REFCLKx - REFCLKx) Phase Qualification A reference clock input fails phase qualification when the phase error at the PFD output exceeds the error window (0.75ns typical) for more than five of eight PFD cycles. A reference clock input is qualified when phase error at the PFD output is within the phase-error window for eight consecutive PFD cycles. Note that phase qualification only applies to the reference input currently being used by the PLL. Frequency Qualification A reference clock input becomes frequency qualified if the input frequency is within 2.4% of the nominal frequency. The reference input becomes frequency disqualified if the input frequency moves away from the nominal frequency by more than 8%. 0V VDT Figure 4. Input Amplitude Detection Threshold 10 ______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Selectable Input Reference Table 1. Divider M Configuration for Input Frequencies CONNECTION FROM DM PIN GND VCC Open 10k to GND INPUT FREQUENCY (MHz) 62.5 125 250 312.5 PLL Out-of-Lock Condition If the frequency difference between the reference clock input and the VCO at the PFD input becomes within 500ppm, the PLL is considered to be in lock (LOCK = 0). When the frequency difference between the reference clock input and the VCO at the PFD input becomes greater than 800ppm, the PLL is considered out-of-lock. It should be noted that the LOCK indicator is not part of the frequency qualification used for the INxFAIL indicators. MAX3671 Table 2. Divider A Configuration for A-Group Output Frequencies CONNECTION FROM DA PIN GND VCC Open 10k to GND OUTPUT FREQUENCY AT OUTA[3:0] (MHz) 62.5 125 156.25 312.5 Input and Output Frequencies The MAX3671 input and output dividers are configured using four-level control inputs DM, DA, and DB. Each divider is independent and can have a unique setting. The input connection and associated frequencies are listed in Tables 1, 2, and 3. Output-Enable Controls Each output group (A and B) has a three-level control input OUTA_EN and OUTB_EN. See Tables 4 and 5 for configuration settings. When clock outputs are disabled, they are high impedance. Unused enabled outputs should be left open. Table 3. Divider B Configuration for B-Group Output Frequencies CONNECTION FROM DB PIN GND VCC Open 10k to GND OUTPUT FREQUENCY AT OUTB[4:0] (MHz) 62.5 125 250 312.5 Power-On-Reset (POR) At power-on, an internal signal is generated to hold the MAX3671 in a reset state. This internal reset time is about 20s after VCC reaches 3.0V (Figure 2). During the POR time, the outputs are held to logic-low (OUTxx = low and OUTxx = high). See Table 6 for output signal status during POR. After this internal reset time, the PLL starts to lock to the reference clock selected by SEL_CLK. A-GROUP OUTPUT DISABLED TO HIGH IMPEDANCE -- OUTA0, OUTA1, OUTA2, OUTA3 OUTA2, OUTA3 Table 4. OUTA[3:0] Enable Control CONNECTION FROM OUTA_EN PIN GND VCC* Open A-GROUP OUTPUT ENABLED OUTA0, OUTA1, OUTA2, OUTA3 -- OUTA0, OUTA1 *Connecting both OUTA_EN and OUTB_EN to VCC enables a factory test mode and forces all indicators to GND. This is not a valid mode of operation. Table 5. OUTB[4:0] Enable Control CONNECTION FROM OUTB_EN PIN GND VCC* Open B-GROUP OUTPUT ENABLED OUTB0, OUTB1, OUTB2, OUTB3, OUTB4 OUTB0 OUTB0, OUTB1, OUTB2 B-GROUP OUTPUT DISABLED TO HIGH IMPEDANCE -- OUTB1, OUTB2, OUTB3, OUTB4 OUTB3, OUTB4 *Connecting both OUTA_EN and OUTB_EN to VCC enables a factory test mode and forces all indicators to GND. This is not a valid mode of operation. ______________________________________________________________________________________ 11 Low-Jitter Frequency Synthesizer with Selectable Input Reference MAX3671 Master Reset After power-up, an external master reset (MR) can be provided to reset the internal dividers. This input requires a minimum reset pulse width of 100ns (active low) and is asynchronous to the reference clock. While MR is low, all clock outputs are held to logic-low (OUTxx = low, OUTxx = high). See Table 6 for the output signal status during master reset. When the master reset input is deasserted (MR = 1), the PLL starts to lock to the reference clock selected by SEL_CLK. Master reset is only needed for applications where divider configurations are changed on the fly and the clock outputs need to maintain phase alignment. A master reset is not required at power-up. Applications Information Interfacing with LVPECL Inputs Figure 5 shows the equivalent LVPECL input circuit for REFCLK0, REFCLK1, and FB_IN. These inputs are internally biased to allow AC- or DC-coupling and have > 40k differential input impedance. When AC-coupled, these inputs can accept LVDS, CML, and LVPECL signals. Unused reference clock inputs should be left open. Interfacing with LVPECL Outputs Figure 6 shows the equivalent LVPECL output circuit. These outputs are designed to drive a pair of 50 transmission lines terminated with 50 to VTT = VCC 2V. If a separate termination voltage (VTT) is not available, other termination methods can be used such as those shown in Figures 7 and 8. Unused outputs, enabled or disabled, can be left open or properly terminated. For more information on LVPECL terminations and how to interface with other logic families, refer to Application Note 291: HFAN-01.0: Introduction to LVDS, PECL, and CML. External Feedback for Zero-Delay Buffer The MAX3671 can be operated with either internal or external PLL feedback path, controlled by the FB_SEL input. Connecting FB_SEL to GND selects internal feedback. For applications where a known phase relationship between the reference clock input and the external feedback input (FB_IN, FB_IN) are needed for phase synchronization, connect FB_SEL to VCC for zero-delay buffer configuration and provide external feedback to the FB_IN input. Layout Considerations The clock inputs and outputs are critical paths for the MAX3671, and care should be taken to minimize discontinuities on the transmission lines. Maintain 100 differential (or 50 single-ended) impedance in and out of the MAX3671. Avoid using vias and sharp corners. Termination networks should be placed as close as possible to receiving clock inputs. Provide space between differential output pairs to reduce crosstalk, especially if the A and B group outputs are operating at different frequencies. PLL Bypass Mode PLL bypass mode is provided for test purposes. In PLL bypass mode (PLL_BYPASS = 1), the selected reference clock is connected to the LVPECL clock outputs directly. The output clock frequency is the same as the input clock frequency and the clock qualification function is not valid. To reduce spurious jitter in bypass mode, the internal VCO should be disabled by shorting the CREG pin to GND. Table 6. Output Signal Status During Power-On-Reset or Master Reset OUTPUT IN0FAIL IN1FAIL LOCK OUTA[3:0] OUTB[4:0] DURING POWER-ON-RESET (FOR ~ 20s AFTER VCC > 3.0V) 1 1 1 Logic-Low Logic-Low DURING MASTER RESET (MR = 0) NOTES Forced high regardless of reference input qualification. Forced high regardless of reference input qualification. PLL out-of-lock. -- -- 12 ______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Selectable Input Reference Power Supply and Ground Connections The MAX3671 has seven supply connection pins; installation of a bypass capacitor at each supply pin is recommended. All seven supply connections should be driven from the same source to eliminate the possibility of independent power-supply sequencing. Excessive supply noise can result in increased jitter. The 56-pin TQFN package features an exposed pad (EP), which provides a low-resistance thermal path for heat removal from the IC and must be connected to the circuit board ground plane for proper operation. MAX3671 VCC VCC VCC - 1.34V > 20k 200 REFCLKx, FB_IN 200 REFCLKx, FB_IN > 20k ESD STRUCTURES MAX3671 Figure 5. Equivalent LVPECL Input Circuit VCC +3.3V +3.3V 130 Z = 50 +3.3V 130 +3.3V LVPECL OUTxx Z = 50 82 OUTxx 82 LVPECL ESD STRUCTURES Figure 7. Thevenin Equivalent LVPECL Termination MAX3671 Figure 6. Equivalent LVPECL Output Circuit ______________________________________________________________________________________ 13 Low-Jitter Frequency Synthesizer with Selectable Input Reference MAX3671 +3.3V 0.1F Z = 50 50 LVPECL 0.1F 0.1F Z = 50 150 150 50 LVPECL +3.3V Figure 8. AC-Coupled LVPECL Termination Pin Configuration TOP VIEW PLL_BYPASS IN1FAIL RSVD4 RSVD3 OUTA0 OUTA0 OUTA1 LOCK GND VCC VCC GND OUTA1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 IN0FAIL 1 RSVD1 2 RSVD2 3 REFCLK0 4 REFCLK0 5 DM 6 VCC 7 GND 8 MR 9 REFCLK1 10 REFCLK1 11 SEL_CLK 12 VCC_VCO 13 GND 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 FB_SEL CPLL OUTB0 OUTB0 OUTB1 OUTB1 OUTB2 OUTB2 FB_IN FB_IN CREG GND VCC DB EP* MAX3671 42 GND 41 VCC 40 OUTA2 39 OUTA2 38 OUTA3 37 OUTA3 36 OUTA_EN 35 OUTB_EN 34 OUTB4 33 OUTB4 32 OUTB3 31 OUTB3 30 VCC 29 GND THIN QFN (8mm x 8mm x 0.8mm) *THE EXPOSED PAD OF THE TQFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND ELECTRICAL OPERATION. 14 ______________________________________________________________________________________ DA Low-Jitter Frequency Synthesizer with Selectable Input Reference Typical Application Circuits +3.3V 0.1F MAX3671 0.1F CPLL CREG 0.1F Z = 50 62.5MHz BACKPLANE REFERENCE CLOCK 0.1F Z = 50 50 REFCLK0 0.22F VCC VCC_VCO 0.1F OUTA3 Z = 50 50 10GE PHY 156.25MHz 0.1F 50 REFCLK0 OUTA3 150 150 0.1F Z = 50 50 0.1F REFCLK1 MAX3671 OUTA0 0.1F Z = 50 156.25MHz REFCLK1 50 10GE PHY 0.1F 0.1F OUTA0 150 DM DA +3.3V DB OUTA_EN OUTB_EN OUTB4 150 Z = 50 50 0.1F Z = 50 125MHz 50 GBE PHY 0.1F 0.1F OUTB4 150 SEL_CLK PLL_BYPASS 0.1F FB_IN FB_IN FB_SEL MR OUTB0 Z = 50 50 125MHz 150 Z = 50 50 0.1F 0.1F IN0FAIL IN1FAIL OUTB0 GND EP 150 150 Z = 50 LOCK 50 GBE PHY ______________________________________________________________________________________ 15 Low-Jitter Frequency Synthesizer with Selectable Input Reference MAX3671 Typical Application Circuits (continued) 4 x 156.25MHz 62.5MHz OUTA[3:0] MAX3671 8kHz IN0 CLK0 62.5MHz REFCLK0 OUTB[4:0] 5 x 125MHz MAX9450 8kHz IN1 OUTA[3:0] 4 x 156.25MHz MAX3671 QA 25MHz 125MHz REFCLK0 OUTB[4:0] 5 x 312.5MHz MAX3624 QB[1:0] 2 x 125MHz Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 56 TQFN-EP PACKAGE CODE T5688+3 DOCUMENT NO. 21-0135 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. |
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